For electronics systems such as computer systems, it is typically necessary to provide one or more system components with the ability to selectively enable the operation of other system components. For example, a system controller or "master" such as a microprocessor may need to enable another system component or "agent" such as a memory chip in order to gain access to the data stored by the memory chip. Device selection is useful in many other systems and circumstances, as well.
There are a number of alternative methods for providing device selection in an electronics or computer system, and each method has an associated cost of implementation. For example, the master and agent devices must typically include additional pins for asserting and accepting selection or enable signals, and there are costs associated with providing semiconductor die space for these pins and supporting circuitry. Similarly, there are costs associated with providing printed circuit (PC) board space for routing the selection or enable signals between the master and agent devices.
FIG. 1 shows a system 10 that implements a prior device selection scheme wherein selection bus 15 transmits a binary encoded identification number from master 20 to select one of agents 21-36 so that master 20 may access the selected agent via data bus 48. To support device selection according to this method, each of agents 21-36 must be provided with (1) a unique identification number such as I.D. NO. 45 of agent 21 and (2) comparator circuitry 40 for comparing the transmitted identification number to the agent's identification number. In a system supporting a maximum of 2.sup.N agents, the width of selection bus 15 is N bits, and master 20 and agents 21-36 must each have N pins dedicated or multiplexed for device selection.
The number of output pins required for master 20 is minimized according to the scheme of FIG. 1; however, the total number of input pins required for agents 21-36 is maximized.
FIG. 2 shows a system 50 that implements another prior device selection scheme. A selection bus 55 transmits a binary encoded identification number (shown as BIT 0-BIT 3) and its complement (shown as BIT 0-BIT 3) from master 60 to select one of agents 61-76 so that master 60 may access the selected agent via data bus 54. The assertion or deassertion of the select signals for the complementary identification number (BIT 0-BIT 3) directly depends on the value of the true identification number (BIT 0-BIT 3) . To support device selection according to this method, each of agents 61-76 must be provided with majority logic circuitry such as a logical AND gate 52. In a system supporting a maximum of 2.sup.N agents, the width of the selection bus 55 is 2N bits, master 60 must have 2N output pins for device selection, and agents 61-76 must each have N input pins for device selection.
Device selection by the system of FIG. 2 is typically faster than that of FIG. 1 because majority logic circuitry is typically faster than comparators. Furthermore, agents need not be assigned identification numbers. The number of output pins required by the master to support device selection and the number of conductors for the selection bus are both doubled. Therefore, this prior art scheme is typically applied to systems with a limited (e.g. four) number of agents.
FIG. 3 shows a system 80 that implements another prior device selection scheme wherein each of a plurality of enable lines 85 are routed from master 90 to a corresponding one of agents 91-106 so that master 90 may enable and access the selected agent via data bus 115. To support device selection according to this method, master 90 must be provided with a 1-of-16 decoder circuit 110 that accepts a binary number and asserts one of the sixteen enable signals EN1-EN16. In a system supporting a maximum of 2.sup.N agents, master 90 must have a 1-of-N decoder providing 2.sup.N enable signals on 2.sup.N lines. Each of the 2.sup.N agents must have one input pin for device selection. Master 90 must have 2.sup.N output pins for device selection.
The total number of input pins required for the agent devices is minimized according to the scheme of FIG. 3; however, the number of output pins required for the master device is maximized. An alternative scheme would place the 1-of-16 decoder circuit 100 external to master 90, thus reducing the number of output pins for device selection by master 90. Providing the 1-of-16 decoder circuit 100 as a separate device would slow the process of device selection by an undesirable amount for some systems.